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mikroSDK Reference Manual
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mikroSDK Reference Manual
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Macros | |
| #define | STMPE811_REG_ADDR_CHIP_ID ((uint8_t)0x00) |
| STMPE811 Device identification Register. More... | |
| #define | STMPE811_REG_ADDR_ID_VER ((uint8_t)0x02) |
| STMPE811 register for revision number engineering sample final silicon. More... | |
| #define | STMPE811_REG_ADDR_SYS_CTRL1 ((uint8_t)0x03) |
| STMPE811 register for reset control. More... | |
| #define | STMPE811_REG_ADDR_SYS_CTRL2 ((uint8_t)0x04) |
| STMPE811 register for clock control. More... | |
| #define | STMPE811_REG_ADDR_SPI_CFG ((uint8_t)0x08) |
| STMPE811 register for SPI interface configuration. More... | |
| #define | STMPE811_REG_ADDR_INT_CTRL ((uint8_t)0x09) |
| STMPE811 Device identification Register. More... | |
| #define | STMPE811_REG_ADDR_INT_EN ((uint8_t)0x0A) |
| STMPE811 interrupt enable register. More... | |
| #define | STMPE811_REG_ADDR_INT_STA ((uint8_t)0x0B) |
| STMPE811 interrupt status register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_EN ((uint8_t)0x0C) |
| STMPE811 GPIO interrupt enable register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_INT_STA ((uint8_t)0x0D) |
| STMPE811 GPIO interrupt status register. More... | |
| #define | STMPE811_REG_ADDR_ADC_INT_EN ((uint8_t)0x0E) |
| STMPE811 ADC interrupt enable register. More... | |
| #define | STMPE811_REG_ADDR_ADC_INT_STA ((uint8_t)0x0F) |
| STMPE811 ADC interrupt status register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_SET_PIN ((uint8_t)0x10) |
| STMPE811 GPIO set pin register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_CLR_PIN ((uint8_t)0x11) |
| STMPE811 GPIO clear pin register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_MP_STA ((uint8_t)0x12) |
| STMPE811 monitor pin state register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_DIR ((uint8_t)0x13) |
| STMPE811 GPIO direction register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_ED ((uint8_t)0x14) |
| STMPE811 GPIO edge detect register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_RE ((uint8_t)0x15) |
| STMPE811 GPIO rising edge register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_FE ((uint8_t)0x16) |
| STMPE811 GPIO falling edge register. More... | |
| #define | STMPE811_REG_ADDR_GPIO_AF ((uint8_t)0x17) |
| STMPE811 Alternate function register. More... | |
| #define | STMPE811_REG_ADDR_ADC_CTRL1 ((uint8_t)0x20) |
| STMPE811 0x1C ADC control register. More... | |
| #define | STMPE811_REG_ADDR_ADC_CTRL2 ((uint8_t)0x21) |
| STMPE811 0x01 ADC control register. More... | |
| #define | STMPE811_REG_ADDR_ADC_CAPT ((uint8_t)0x22) |
| STMPE811 ADC data acquisition register. More... | |
| #define | STMPE811_REG_ADDR_ADC_DATA_CH0 ((uint8_t)0x30) |
| STMPE811 register for ADC channel 0. More... | |
| #define | STMPE811_REG_ADDR_ADC_DATA_CH1 ((uint8_t)0x32) |
| STMPE811 register for ADC channel 1. More... | |
| #define | STMPE811_REG_ADDR_ADC_DATA_CH2 ((uint8_t)0x34) |
| STMPE811 register for ADC channel 2. More... | |
| #define | STMPE811_REG_ADDR_ADC_DATA_CH3 ((uint8_t)0x36) |
| STMPE811 register for ADC channel 3. More... | |
| #define | STMPE811_REG_ADDR_ADC_DATA_CH4 ((uint8_t)0x38) |
| STMPE811 register for ADC channel 4. More... | |
| #define | STMPE811_REG_ADDR_ADC_DATA_CH5 ((uint8_t)0x3A) |
| STMPE811 register for ADC channel 5. More... | |
| #define | STMPE811_REG_ADDR_ADC_DATA_CH6 ((uint8_t)0x3C) |
| STMPE811 register for ADC channel 6. More... | |
| #define | STMPE811_REG_ADDR_ADC_DATA_CH7 ((uint8_t)0x3E) |
| STMPE811 register for ADC channel 7. More... | |
| #define | STMPE811_REG_ADDR_TSC_CTRL ((uint8_t)0x40) |
| STMPE811 touchscreen controller setup register. More... | |
| #define | STMPE811_REG_ADDR_TSC_CFG ((uint8_t)0x41 |
| STMPE811 touchscreen controller configuration register. More... | |
| #define | STMPE811_REG_ADDR_WDW_TR_X ((uint8_t)0x42) |
| STMPE811 window setup for top right X register. More... | |
| #define | STMPE811_REG_ADDR_WDW_TR_Y ((uint8_t)0x44) |
| STMPE811 window setup for top right Y register. More... | |
| #define | STMPE811_REG_ADDR_WDW_BL_X ((uint8_t)0x46) |
| STMPE811 window setup for bottom left X register. More... | |
| #define | STMPE811_REG_ADDR_WDW_BL_Y ((uint8_t)0x48) |
| STMPE811 window setup for bottom left Y register. More... | |
| #define | STMPE811_REG_ADDR_FIFO_TH ((uint8_t)0x4A) |
| STMPE811 FIFO level register. More... | |
| #define | STMPE811_REG_ADDR_FIFO_STA ((uint8_t)0x4B) |
| STMPE811 current status of FIFO register. More... | |
| #define | STMPE811_REG_ADDR_FIFO_SIZE ((uint8_t)0x4C) |
| STMPE811 current filled level of FIFO register. More... | |
| #define | STMPE811_REG_ADDR_TSC_DATA_X ((uint8_t)0x4D) |
| STMPE811 touchscreen controller data access register. More... | |
| #define | STMPE811_REG_ADDR_TSC_DATA_Y ((uint8_t)0x4F) |
| STMPE811 touchscreen controller data access register. More... | |
| #define | STMPE811_REG_ADDR_TSC_DATA_Z ((uint8_t)0x51) |
| STMPE811 touchscreen controller data access register. More... | |
| #define | STMPE811_REG_ADDR_TSC_DATA_XYZ ((uint8_t)0x52) |
| STMPE811 touchscreen controller data access register. More... | |
| #define | STMPE811_REG_ADDR_TSC_FRACTION_Z ((uint8_t)0x56) |
| STMPE811 Touchscreen controller FRACTION_Z register. More... | |
| #define | STMPE811_REG_ADDR_TSC_DATA ((uint8_t)0x57) |
| STMPE811 touchscreen controller data access register. More... | |
| #define | STMPE811_REG_ADDR_TSC_I_DRIVE ((uint8_t)0x58) |
| STMPE811 touchscreen controller drive I register. More... | |
| #define | STMPE811_REG_ADDR_TSC_SHIELD ((uint8_t)0x59) |
| STMPE811 touchscreen controller shield register. More... | |
| #define | STMPE811_REG_ADDR_TEMP_CTRL ((uint8_t)0x60) |
| STMPE811 temperature sensor setup register. More... | |
| #define | STMPE811_REG_ADDR_TEMP_DATA ((uint8_t)0x61) |
| STMPE811 temperature data access port register. More... | |
| #define | STMPE811_REG_ADDR_TEMP_TH ((uint8_t)0x62) |
| STMPE811 temperature controlled interruprt register. More... | |
STMPE811 registers description.
| #define STMPE811_REG_ADDR_CHIP_ID ((uint8_t)0x00) |
16 bit read only only register Device identification. Value after reset: 0x0811.
| #define STMPE811_REG_ADDR_ID_VER ((uint8_t)0x02) |
8 bit read only register for revision number engineering sample final silicon, value : 0x03.
| #define STMPE811_REG_ADDR_SYS_CTRL1 ((uint8_t)0x03) |
8 bit read/write register for reset control. Value after reset 0x00
| #define STMPE811_REG_ADDR_SYS_CTRL2 ((uint8_t)0x04) |
8 bit read/write register for clock control. Value after reset: 0x0F.
| #define STMPE811_REG_ADDR_SPI_CFG ((uint8_t)0x08) |
8 bit read/write register for SPI interface configuration. Value after reset 0x01
| #define STMPE811_REG_ADDR_INT_CTRL ((uint8_t)0x09) |
8 bit read/write interrupt control register.
| #define STMPE811_REG_ADDR_INT_EN ((uint8_t)0x0A) |
8 bit read/write interrupt enable register.
| #define STMPE811_REG_ADDR_INT_STA ((uint8_t)0x0B) |
8 bit read only interrupt status register.
| #define STMPE811_REG_ADDR_GPIO_EN ((uint8_t)0x0C) |
8 bit read/write GPIO interrupt enable register.
| #define STMPE811_REG_ADDR_GPIO_INT_STA ((uint8_t)0x0D) |
8 bit read only GPIO interrupt status register.
| #define STMPE811_REG_ADDR_ADC_INT_EN ((uint8_t)0x0E) |
8 bit read/write ADC interrupt enable register.
| #define STMPE811_REG_ADDR_ADC_INT_STA ((uint8_t)0x0F) |
8 bit read only ADC interrupt status register.
| #define STMPE811_REG_ADDR_GPIO_SET_PIN ((uint8_t)0x10) |
8 bit read/write GPIO set pin register.
| #define STMPE811_REG_ADDR_GPIO_CLR_PIN ((uint8_t)0x11) |
8 bit read/write GPIO clear pin register.
| #define STMPE811_REG_ADDR_GPIO_MP_STA ((uint8_t)0x12) |
8 bit read/write GPIO monitor pin state register.
| #define STMPE811_REG_ADDR_GPIO_DIR ((uint8_t)0x13) |
8 bit read/write GPIO direction register.
| #define STMPE811_REG_ADDR_GPIO_ED ((uint8_t)0x14) |
8 bit read/write GPIO edge detect register.
| #define STMPE811_REG_ADDR_GPIO_RE ((uint8_t)0x15) |
8 bit read/write GPIO rising edge register.
| #define STMPE811_REG_ADDR_GPIO_FE ((uint8_t)0x16) |
8 bit read/write GPIO falling edge register.
| #define STMPE811_REG_ADDR_GPIO_AF ((uint8_t)0x17) |
8 bit read/write Alternate function register.
| #define STMPE811_REG_ADDR_ADC_CTRL1 ((uint8_t)0x20) |
8 bit read/write 0x1C ADC control register.
| #define STMPE811_REG_ADDR_ADC_CTRL2 ((uint8_t)0x21) |
8 bit read/write 0x01 ADC control register.
| #define STMPE811_REG_ADDR_ADC_CAPT ((uint8_t)0x22) |
8 bit read/write xFF To initiate ADC data acquisition.
| #define STMPE811_REG_ADDR_ADC_DATA_CH0 ((uint8_t)0x30) |
16 bit read only register for ADC channel 0.
| #define STMPE811_REG_ADDR_ADC_DATA_CH1 ((uint8_t)0x32) |
16 bit read only register for ADC channel 1 STMPE811 registers STMPE811 20/66 Doc ID 14489 Rev 5.
| #define STMPE811_REG_ADDR_ADC_DATA_CH2 ((uint8_t)0x34) |
16 bit read only register for ADC channel 2.
| #define STMPE811_REG_ADDR_ADC_DATA_CH3 ((uint8_t)0x36) |
16 bit read only register for ADC channel 3.
| #define STMPE811_REG_ADDR_ADC_DATA_CH4 ((uint8_t)0x38) |
16 bit read only register for ADC channel 4.
| #define STMPE811_REG_ADDR_ADC_DATA_CH5 ((uint8_t)0x3A) |
16 bit read only register for ADC channel 5.
| #define STMPE811_REG_ADDR_ADC_DATA_CH6 ((uint8_t)0x3C) |
16 bit read only register for ADC channel 6.
| #define STMPE811_REG_ADDR_ADC_DATA_CH7 ((uint8_t)0x3E) |
16 bit read only register for ADC channel 7.
| #define STMPE811_REG_ADDR_TSC_CTRL ((uint8_t)0x40) |
8 bit read/write 4-wire touchscreen controller setup. Value after reset: 0x90
| #define STMPE811_REG_ADDR_TSC_CFG ((uint8_t)0x41 |
) 8 bit read/write Touchscreen controller configuration. Value after reset: 0x00
| #define STMPE811_REG_ADDR_WDW_TR_X ((uint8_t)0x42) |
16 bit read/write Window setup for top right X. Value after reset: 0x0fff
| #define STMPE811_REG_ADDR_WDW_TR_Y ((uint8_t)0x44) |
16 bit read/write Window setup for top right Y. Value after reset: 0x0fff
| #define STMPE811_REG_ADDR_WDW_BL_X ((uint8_t)0x46) |
16 bit read/write Window setup for bottom left X. Value after reset: 0x0000
| #define STMPE811_REG_ADDR_WDW_BL_Y ((uint8_t)0x48) |
16 bit read/write Window setup for bottom left Y. Value after reset: 0x0000
| #define STMPE811_REG_ADDR_FIFO_TH ((uint8_t)0x4A) |
8 bit read/write FIFO level to generate interrupt. Value after reset: 0x00
| #define STMPE811_REG_ADDR_FIFO_STA ((uint8_t)0x4B) |
8 bit read/write Current status of FIFO. Value after reset: 0x20
| #define STMPE811_REG_ADDR_FIFO_SIZE ((uint8_t)0x4C) |
8 bit read only Current filled level of FIFO.
| #define STMPE811_REG_ADDR_TSC_DATA_X ((uint8_t)0x4D) |
16 bit read only Data port for touchscreen controller data access.
| #define STMPE811_REG_ADDR_TSC_DATA_Y ((uint8_t)0x4F) |
16 bit read only Data port for touchscreen controller data access.
| #define STMPE811_REG_ADDR_TSC_DATA_Z ((uint8_t)0x51) |
8 bit read only Data port for touchscreen controller data access.
| #define STMPE811_REG_ADDR_TSC_DATA_XYZ ((uint8_t)0x52) |
32 bit read only Data port for touchscreen controller data access.
| #define STMPE811_REG_ADDR_TSC_FRACTION_Z ((uint8_t)0x56) |
8 bit Touchscreen controller FRACTION_Z. Value after reset: 0x00
| #define STMPE811_REG_ADDR_TSC_DATA ((uint8_t)0x57) |
8 bit read only register. Data port for touchscreen controller data access. Value after reset: 0x00
| #define STMPE811_REG_ADDR_TSC_I_DRIVE ((uint8_t)0x58) |
8 bit read/write register. Touchscreen controller drive I. Value after reset: 0x00
| #define STMPE811_REG_ADDR_TSC_SHIELD ((uint8_t)0x59) |
8 bit read/write register. Touchscreen controller shield. Value after reset: 0x00
| #define STMPE811_REG_ADDR_TEMP_CTRL ((uint8_t)0x60) |
8 bit read/write register. Temperature sensor setup. Value after reset: 0x00
| #define STMPE811_REG_ADDR_TEMP_DATA ((uint8_t)0x61) |
8 bit read only register. Temperature data access port. Value after reset: 0x00
| #define STMPE811_REG_ADDR_TEMP_TH ((uint8_t)0x62) |
8 bit read/write register. Threshold for temperature controlled interrupt. Value after reset: 0x00
1.8.16