drv_dma.h

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#ifndef _DRV_DMA_H_
#define _DRV_DMA_H_
 
#ifdef __cplusplus
extern "C"{
#endif
 
#include "drv_name.h"
#include "hal_dma.h"
 
typedef enum
{
 DMA_SUCCESS = 0, 
 DMA_ERROR = (-1) 
} dma_err_t;
 
typedef enum
{
 DMA_STATE_FREE = 0, 
 DMA_STATE_ALLOCATED 
} dma_state_t;
 
typedef enum
{
 DMA_SOURCE_MEMORY_REGION_RAM = 0, 
 DMA_SOURCE_MEMORY_REGION_PFM = 1, 
 DMA_SOURCE_MEMORY_REGION_DEEPROM = 2 
} dma_source_memory_region_t;
 
typedef enum
{
 DMA_DIRECTION_MEMORY_TO_MEMORY = 0, 
 DMA_DIRECTION_MEMORY_TO_PERIPH, 
 DMA_DIRECTION_PERIPH_TO_MEMORY, 
 DMA_DIRECTION_PERIPH_TO_PERIPH, 
 DMA_DIRECTION_DEFAULT = DMA_DIRECTION_MEMORY_TO_MEMORY 
} dma_direction_t;
 
typedef enum
{
 DMA_DATA_ALIGN_BYTES_1 = 0, 
 DMA_DATA_ALIGN_BYTES_2, 
 DMA_DATA_ALIGN_BYTES_3, 
 DMA_DATA_ALIGN_BYTES_4, 
 DMA_DATA_ALIGN_DEFAULT = DMA_DATA_ALIGN_BYTES_1 
} dma_data_align_t;
 
typedef enum
{
 DMA_MODE_NORMAL = 0, 
 DMA_MODE_CIRCULAR, 
 DMA_MODE_DEFAULT = DMA_MODE_NORMAL 
} dma_mode_t;
 
typedef enum
{
 DMA_PRIORITY_LOW = 0, 
 DMA_PRIORITY_MEDIUM, 
 DMA_PRIORITY_HIGH, 
 DMA_PRIORITY_VERY_HIGH, 
 DMA_PRIORITY_DEFAULT = DMA_PRIORITY_MEDIUM 
} dma_priority_t;
 
typedef enum
{
 DMA_BURST_SIZE_INCREMENT_1 = 0, 
 DMA_BURST_SIZE_INCREMENT_2, 
 DMA_BURST_SIZE_INCREMENT_4, 
 DMA_BURST_SIZE_INCREMENT_8, 
 DMA_BURST_SIZE_INCREMENT_16, 
 DMA_BURST_SIZE_INCREMENT_32, 
 DMA_BURST_SIZE_INCREMENT_DEFAULT = DMA_BURST_SIZE_INCREMENT_1 
} dma_burst_size_t;
 
typedef uint8_t dma_channel_t[ DMA_NUM_OF_MODULES ][ DMA_NUM_OF_STREAMS_FAMILY ][ DMA_NUM_OF_CHANNELS_FAMILY ];
 
typedef struct
{
 uint8_t module; 
 uint8_t stream; 
 uint8_t channel; 
 dma_direction_t direction; 
 dma_mode_t mode; 
 bool src_inc; 
 dma_data_align_t data_align_source; 
 dma_burst_size_t burst_size_source; 
 bool dst_inc; 
 dma_data_align_t data_align_destination;
 dma_burst_size_t burst_size_destination;
 dma_priority_t priority; 
 uint32_t addr_src; 
 uint32_t addr_dst; 
 size_t transfer_length; 
} dma_config_t;
 
typedef struct
{
 handle_t handle; 
 dma_config_t config; 
 uint8_t module; 
 uint8_t stream; 
 uint8_t channel; 
 dma_state_t allocated; 
 bool initialized; 
} dma_t;
 
void dma_configure_default( dma_config_t *config );
 
err_t dma_open( dma_t *obj, dma_config_t *config );
 
void dma_get_channels( dma_channel_t *channels );
 
err_t dma_set_mode( dma_t *obj, dma_mode_t mode );
 
err_t dma_set_direction( dma_t *obj, dma_direction_t direction );
 
err_t dma_set_priority( dma_t *obj, dma_priority_t priority );
 
err_t dma_set_transfer_config( dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, dma_source_memory_region_t src_mem_type );
 
err_t dma_transfer_start( dma_t *obj );
 
err_t dma_transfer_stop( dma_t *obj );
 
err_t dma_transfer_abort( dma_t *obj );
 
err_t dma_close( dma_t *obj );
 // drvdmagroup // drvgroup // pergroup
 
#ifdef __cplusplus
}
#endif
 
#endif // _DRV_DMA_H_
// ------------------------------------------------------------------------- END