Peripheral Pin Select Library
The Peripheral Pin Select library enables user to have more than one digital peripheral multiplexed on a single pin.
Users may independently map the input and/or output of any one of many digital peripherals to any one of these I/O pins.
The peripherals managed by the Peripheral Pin Select library are all digital only peripherals.
A key difference between pin select and non pin select peripherals is that pin select peripherals are not associated
with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be
used.
In contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
When a pin selectable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin.

Library Routines
Unlock_IOLOCK
Prototype |
void Unlock_IOLOCK(); |
---|---|
Description |
Unlocks I/O pins for Peripheral Pin Mapping. |
Parameters |
None. |
Returns |
Nothing. |
Requires |
Nothing. |
Example |
Unlock_IOLOCK(); |
Notes |
None. |
Lock_IOLOCK
Prototype |
void Lock_IOLOCK(); |
---|---|
Description |
Locks I/O pins for Peripheral Pin Mapping. |
Parameters |
None. |
Returns |
Nothing. |
Requires |
Nothing. |
Example |
Lock_IOLOCK(); |
PPS_Mapping
Prototype |
unsigned PPS_Mapping(unsigned short rp_num, unsigned short direction, unsigned short funct_name); |
---|---|
Description |
Sets desired internal MCU module to be mapped on the requested pins. |
Parameters |
|
Returns |
|
Requires |
Nothing. |
Example |
PPS_Mapping(15, _INPUT, _RX2_DT2) // Sets pin 15 to be Input, and maps RX2/DT2 Input to it PPS_Mapping(5, _OUTPUT, _TX2_CK2); // Sets pin 5 to be Output, and maps EUSART2 Asynchronous Transmit/Synchronous Clock Output to it |
Notes |
Use this routine when |
PPS_Mapping_NoLock
Prototype |
unsigned PPS_Mapping_NoLock(unsigned short rp_num, unsigned short input_output, unsigned short funct_name); |
---|---|
Description |
Sets desired internal MCU module to be mapped on the requested pins. This function doesn't use Unlock_IOLOCK and Lock_IOLOCK routines, so the user must call them before and after this function call (very useful if |
Parameters |
|
Returns |
|
Requires |
Nothing. |
Example |
Unlock_IOLOCK(); PPS_Mapping_NoLock(15, _INPUT, _RX2_DT2); // Sets pin 15 to be Input, and maps RX2/DT2 Input to it PPS_Mapping_NoLock(5, _OUTPUT, _TX2_CK2); // Sets pin 5 to be Output, and maps EUSART2 Asynchronous Transmit/Synchronous Clock Output to it Lock_IOLOCK(); |
Notes |
None. |
Direction Parameters
Direction Parameter | Description |
---|---|
_INPUT | Sets selected pin as input |
_OUTPUT | Sets selected pin as output |
Input Functions
Function Name | Description |
---|---|
_CIRX | ECAN1 Receive |
_COFSI | DCI Frame Sync Input |
_CSCKI | DCI Serial Clock Input |
_CSDI | DCI Serial Data Input |
_FLTA1 | PWM1 Fault |
_FLTA2 | PWM2 Fault |
_FLTA3 | PWM3 Fault |
_FLTA4 | PWM4 Fault |
_FLTA5 | PWM5 Fault |
_FLTA6 | PWM6 Fault |
_FLTA7 | PWM7 Fault |
_FLTA8 | PWM8 Fault |
_IC1 | Input Capture 1 |
_IC2 | Input Capture 2 |
_IC3 | Input Capture 3 |
_IC4 | Input Capture 4 |
_IC5 | Input Capture 5 |
_IC6 | Input Capture 6 |
_IC7 | Input Capture 7 |
_IC8 | Input Capture 8 |
_IC9 | Input Capture 9 |
_INDX1 | QEI1 Index |
_INDX2 | QEI2 Index |
_INT1 | External Interrupt 1 |
_INT2 | External Interrupt 2 |
_INT3 | External Interrupt 3 |
_INT4 | External Interrupt 4 |
_QEA1 | QEI1 Phase A |
_QEA2 | QEI2 Phase A |
_QEB1 | QEI1 Phase B |
_QEB2 | QEI2 Phase B |
_SCK1IN | SPI1 Clock Input |
_SCK2IN | SPI2 Clock Input |
_SCK3IN | SPI3 Clock Input |
_SDI1 | SPI1 Data Input |
_SDI2 | SPI2 Data Input |
_SDI3 | SPI3 Data Input |
_SS1IN | SPI1 Slave Select Input |
_SS2IN | SPI2 Slave Select Input |
_SS3IN | SPI3 Slave Select Input |
_T1CK | Timer1 External Clock |
_T2CK | Timer2 External Clock |
_T3CK | Timer3 External Clock |
_T4CK | Timer4 External Clock |
_T5CK | Timer5 External Clock |
_U1CTS | UART1 Clear To Send |
_U2CTS | UART2 Clear To Send |
_U3CTS | UART3 Clear To Send |
_U4CTS | UART4 Clear To Send |
_U1RX | UART1 Receive |
_U2RX | UART2 Receive |
_U3RX | UART3 Receive |
_U4RX | UART4 Receive |
Output Functions
Function Name | Description |
---|---|
_NULL | The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. |
_ACMP1 | RPn tied to Analog Comparator Output 1 |
_ACMP2 | RPn tied to Analog Comparator Output 2 |
_ACMP3 | RPn tied to Analog Comparator Output 3 |
_ACMP4 | RPn tied to Analog Comparator Output 4 |
_C1OUT | Comparator 1 Output |
_C2OUT | Comparator 2 Output |
_C3OUT | Comparator 3 Output |
_COFSOS | DCI Frame Sync Output |
_CSCKO | DCI Serial Clock Output |
_CSDO | DCI Serial Data Output |
_CTPLS | CTMU Output Pulse |
_C1TX | ECAN1 Transmit |
_OC1 | Output Compare 1 |
_OC2 | Output Compare 2 |
_OC3 | Output Compare 3 |
_OC4 | Output Compare 4 |
_OC5 | Output Compare 5 |
_OC6 | Output Compare 6 |
_OC7 | Output Compare 7 |
_OC8 | Output Compare 8 |
_OC9 | Output Compare 9 |
_OCFA | Output Compare Fault A |
_OCFB | Output Compare Fault B |
_PWM4H | RPn tied to PWM output pins associated with PWM Generator 4 |
_PWM4L | RPn tied to PWM output pins associated with PWM Generator 4 |
_REFCLKO | REFCLK output signal |
_SCK1OUT | SPI1 Clock Output |
_SCK2OUT | SPI2 Clock Output |
_SCK3OUT | SPI3 Clock Output |
_SDO1 | SPI1 Data Output |
_SDO2 | SPI2 Data Output |
_SDO3 | SPI3 Data Output |
_SS1OUT | SPI1 Slave Select Output |
_SS2OUT | SPI2 Slave Select Output |
_SS3OUT | SPI3 Slave Select Output |
_SYNCI1 | External Synchronization signal to PWM Master Time Base |
_SYNCI2 | External Synchronization signal to PWM Master Time Base |
_SYNCO1 | RPn tied to external device synchronization signal via PWM master time base |
_U1RTS | UART1 Request To Send |
_U2RTS | UART2 Request To Send |
_U3RTS | UART3 Request To Send |
_U4RTS | UART4 Request To Send |
_U1TX | UART1 Transmit |
_U2TX | UART2 Transmit |
_U3TX | UART3 Transmit |
_U4TX | UART4 Transmit |
_UPDN | QEI direction (UPDN) status |
_UPDN1 | QEI1 direction (UPDN) status |
_UPDN2 | QEI2 direction (UPDN) status |
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