Quad SPI Master Controller Library
The Quad SPI Master Controller may be used to communicate with various peripheral devices that use a Serial Peripheral Interface, such as EEPROMS, DACs and ADCs.
The controller can be configured to support advanced SPI Flash devices with multi-phase access protocols. Data can be transfered in Half Duplex, Single Data Rate, Dual Data Rate and Quad Data Rate modes.
In all modes and all SPI clock speeds, the controller supports back-to-back reads and writes without clock stretching if internal bandwidth permits. The module is available only for CEC1702 MCU.
Library Routines
spi_port_sel
| Prototype |
void spi_port_sel(char port, char pin_mask, char en);
|
| Description |
This function controls SPI port control. It facilitates the selection of ports and offers enable/disable control.
By selection of ports, the GPIOs and chip selects are configured as necessary.
|
| Parameters |
port: port number. The permitted port numbers are :
| Value |
Description |
| 0 |
Port 0, External shared. |
| 1 |
Port 1, external private (Recovery). |
| 2 |
Port 2, Internal. |
ifctrl: Specifies the pin(s) of the selected Quad SPI Master port that needs to be modified. Value is formed according to this bit scheme :
| Value |
Description |
|
Bit 5
|
IO3. |
|
Bit 4
|
IO2. |
|
Bit 3
|
IO1. |
|
Bit 2
|
IO0. |
|
Bit 1
|
Clock. |
|
Bit 0
|
Chip Select. |
en: enable or disable controller. The permitted values are :
| Value |
Description |
| 0 |
Disable. |
| 1 |
Enable. |
|
| Returns |
Nothing.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
If any port numbers other that the one’s mentioned above are used, the function will not perform any operation.
|
spi_port_drv_slew
| Prototype |
void spi_port_drv_slew(char port, char pin_mask, char drv_slew);
|
| Description |
This function configures the drive strength and slew rate for GPIOs based on selected port.
|
| Parameters |
port: port number. The permitted port numbers are :
| Value |
Description |
| 0 |
Port 0, External shared. |
| 1 |
Port 1, external private (Recovery). |
| 2 |
Port 2, Internal. |
ifctrl: Specifies the pin(s) of the selected Quad SPI Master port that needs to be modified. Value is formed according to this bit scheme :
| Value |
Description |
|
Bit 5
|
IO3. |
|
Bit 4
|
IO2. |
|
Bit 3
|
IO1. |
|
Bit 2
|
IO0. |
|
Bit 1
|
Clock. |
|
Bit 0
|
Chip Select. |
en: set drive strength and slew rate. The permitted values are :
| Value |
Description |
bits 5-4 :
- 0b11 = 12mA
- 0b10 = 8mA
- 0b01 = 4mA
- 0b00 = 2mA
|
Drive strength on the pin. |
bit 0 :
- 0b0 = fast
- 0b1 = slow (half frequency)
|
Slew rate on the pin. |
|
| Returns |
Nothing.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
If any port numbers other that the one’s mentioned above are used, the function will not perform any operation.
|
rom_dis_lock_shd_spi
| Prototype |
void rom_dis_lock_shd_spi(char ock_shd_spi);
|
| Description |
This function applies GPIO Locks as specified in customer section of EFUSE.
|
| Parameters |
lock_shd_spi: lock to be applied. Permitted values :
| Value |
Description |
| 0 |
Do not modify lock values. |
| 1 |
Insure Shared SPI GPIO's are disabled (tri-state input) and these pins are locked. |
|
| Returns |
Nothing.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_init
| Prototype |
void qmspi_init(unsigned long freqHz, unsigned char spi_signalling, unsigned char ifctrl);
|
| Description |
This function configures the frequency of SPI, the mode of operation and interface control.
|
| Parameters |
freqHz: SPI frequency. The permitted frequency values are :
| Value |
Description |
| 48 |
48 MHz SPI frequency. |
| 24 |
24 MHz SPI frequency. |
| 16 |
16 MHz SPI frequency. |
| 12 |
12 MHz SPI frequency. |
spi_signalling: mode of operation. The following modes of operation are permitted :
| Value |
Description |
| SPI_MODE_0 |
Data is sampled at the leading rising edge of the clock. |
| SPI_MODE_1 |
Data is sampled at the trailing falling edge of the clock. |
| SPI_MODE_2 |
Data is sampled at the leading falling edge of the clock. |
| SPI_MODE_3 |
Data is sampled at the trailing rising edge of the clock. |
ifctrl: set SPI interface control. The permitted values are :
| Value |
Description |
Bit 7 :
1: Enable pull-up resistors on Transmit pins while the pins are not driven.0: No pull-up resistors enabled on Transmit pins.
|
Enable/disable pull-up resistors on Transmit pins. |
Bit 6 :
1: Enable pull-down resistors on Transmit pins while the pins are not driven.0: No pull-down resistors enabled on Transmit pins.
|
Enable/disable pull-down resistors on Transmit pins. |
Bit 5 :
1: Enable pull-up resistors on Receive pins while the the SPI Chip Select signal is not asserted.0: No pull-up resistors enabled on Receive pins.
|
Enable/disable pull-up resistors on Receive pins. |
Bit 4 :
1: Enable pull-down resistors on Receive pins while the the SPI Chip Select signal is not asserted.0: No pull-down resistors enabled on Receive pins.
|
Enable/disable pull-down resistors on Receive pins. |
Bit 3 :
1: HOLD SPI Output Port is driven.0: HOLD SPI Output Port is not driven.
|
Drive HOLD SPI Output port. |
Bit 2 :
1: HOLD is driven to 1.0: HOLD is driven to 0.
|
Set the value on the HOLD SPI Output Port if it is driven. |
Bit 1 :
1: WRITE PROTECT SPI Output Port is driven.0: WRITE PROTECT SPI Output Port is not driven.
|
Drive WRITE PROTECT SPI Output Port. |
Bit 0 :
1: WRITE PROTECT is driven to 1.0: WRITE PROTECT is driven to 0.
|
Sets the value on the WRITE PROTECT SPI Output Port if it is driven. |
|
| Returns |
Nothing.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_freq_get
| Prototype |
unsigned long qmspi_freq_get();
|
| Description |
The function call is used to get the frequency of SPI.
|
| Parameters |
None.
|
| Returns |
Returns the SPI operating frequency.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_freq_set
| Prototype |
void qmspi_freq_set(unsigned long freq_hz);
|
| Description |
The function call is used to set the frequency of SPI.
|
| Parameters |
freqHz: SPI frequency. The permitted frequency values are :
| Value |
Description |
| 48 |
48 MHz SPI frequency. |
| 24 |
24 MHz SPI frequency. |
| 16 |
16 MHz SPI frequency. |
| 12 |
12 MHz SPI frequency. |
|
| Returns |
Nothing.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_xfr_done_status
| Prototype |
char qmspi_xfr_done_status(unsigned long* qmspi_status);
|
| Description |
This function gets the status of SPI, updates the status into the pointer passed as argument, and returns the done status by evaluating the status register value.
|
| Parameters |
qmspi_status: pointer to a variable where the status of QMSPI is stored. Bit definition for the status variable is explained below :
| Bit number |
Definition |
| 0 |
XFR_COMPLETE |
| 1 |
DMA_COMPLETE. |
| 2 |
TX_BUFF_ERR |
| 3 |
RX_BUFF_ERR |
| 4 |
PROG_ERR |
| 8 |
TX_BUFF_FULL. |
| 9 |
TX_BUFF_EMPTY |
| 10 |
TX_BUFF_REQ |
| 11 |
TX_BUFF_STALL |
| 12 |
RX_BUFF_FULL. |
| 13 |
RX_BUFF_EMPTY |
| 15 |
RX_BUFF_STALL |
| 16 |
XFR_ACTIVE |
|
| Returns |
1 - if done status is set.0 - otherwise.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_start
| Prototype |
void qmspi_start(unsigned int Ien_mask);
|
| Description |
This function starts the SPI operation with the specified interrupt mask.
|
| Parameters |
Ien_mask: specifies the interrupt mask. The bit definition of interrupt enable mask corresponds to Status register bit definitions mentioned in qmspi_xfr_done_status. Refer data sheet for available interrupts.
|
| Returns |
Nothing.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_start_dma
| Prototype |
void qmspi_start_dma(unsigned char dma_chan, unsigned int ien_mask);
|
| Description |
The function starts SPI operations along with a DMA channel.
|
| Parameters |
dma_chan: DMA Channel selection. Valid values :
| Value |
Channel Name |
| 0 |
DMA_CH00_ID |
| 1 |
DMA_CH01_ID |
| 2 |
DMA_CH02_ID |
| 3 |
DMA_CH03_ID |
| 4 |
DMA_CH04_ID |
| 5 |
DMA_CH05_ID |
| 6 |
DMA_CH06_ID |
| 7 |
DMA_CH07_ID |
| 8 |
DMA_CH08_ID |
| 9 |
DMA_CH09_ID |
| 10 |
DMA_CH10_ID |
| 11 |
DMA_CH12_ID |
| 12 |
DMA_CH12_ID |
| 13 |
DMA_CH13_ID |
Ien_mask: specifies the interrupt mask. The bit definition of interrupt enable mask corresponds to Status register bit definitions mentioned in qmspi_xfr_done_status. Refer data sheet for available interrupts.
|
| Returns |
Nothing.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_cfg_spi_cmd
| Prototype |
unsigned char qmspi_cfg_spi_cmd(unsigned long spi_cmd, unsigned long spi_address);
|
| Description |
This routine configures the QMSPI controller.
|
| Parameters |
Spi_cmd: SPI configuration. Valid values :
| Bit Range |
Description |
| 7:0 |
SPI op-code |
| 9:8 |
cmd bus width. Valid values :
0b00 = 1X -> 8 clocks/byte,0b01 = 2X -> 4 clocks/byte,0b10 = 4X -> 2 clocks/byte.
|
| 11:10 |
address bus width |
| 13:12 |
data bus width |
| 14 |
0 (24-bit address), 1(32-bit address) |
| 15 |
1 use mode byte |
| 23:16 |
mode byte |
| 31:24 |
Number of dummy clocks expressed as number of bytes where : Clocks = bytes * clocks/byte. Clocks per byte depend upon data bus width.
Example: 4X 24bit read 0x6B requires 8 dummy clocks. At 2 clocks/byte, 4 bytes.
The SPI address can be either 24 bit address or 32 bit address.
|
spi_address: specifies the SPI address.
|
| Returns |
The function returns the ID of the Last Descriptor used (Descriptor is a Hardware register, refer data sheet for more details).
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_read_dma
| Prototype |
unsigned long qmspi_read_dma(unsigned long spi_cmd, unsigned long spi_address, unsigned long mem_addr, unsigned long nbytes, unsigned char dma_chan);
|
| Description |
This routine configures the QMSPI controller to read a specified number of bytes from a specified address.
|
| Parameters |
Spi_cmd: specifies the SPI Command. For spi_cmd bit definitions, please refer to the qmspi_cfg_spi_cmd function.Spi_address: specifies the SPI address.Mem_addr: address from where the data is to be read.Nbytes: number of bytes to be read.dma_chan: specifies the DMA Channel to be used. Refer to the qmspi_start_dma function for dmach_id description.
|
| Returns |
The function returns the number of read bytes.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
- If
nbytes is 0, the value returned will be zero.
- If
mem_addr is specified as zero, the function will return a zero.
|
qmspi_write_dma
| Prototype |
unsigned long qmspi_write_dma(unsigned long spi_cmd, unsigned long spi_address, unsigned long mem_addr, unsigned long nbytes, unsigned char dma_chan);
|
| Description |
This routine configures the QMSPI controller to read a specified number of bytes from a specified address.
|
| Parameters |
Spi_cmd: specifies the SPI Command. For spi_cmd bit definitions, please refer to the qmspi_cfg_spi_cmd function.Spi_address: specifies the SPI address.Mem_addr: address at which the data ought to be written.Nbytes: number of bytes to be written.dma_chan: specifies the DMA Channel to be used. Refer to the qmspi_start_dma function for dmach_id description.
|
| Returns |
The function returns the number of written bytes.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
- If
nbytes is 0, the value returned will be zero.
- If
mem_addr is specified as zero, the function will return a zero.
|
qmspi_xmit_cmd
| Prototype |
char qmspi_xmit_cmd(unsigned char* cmd_params, unsigned char ntx, unsigned char nresponse);
|
| Description |
This function is used to send small commands to the flash.
|
| Parameters |
cmd_params pointer to a set of Flash commands. Valid values :
| Value |
Command |
| 0x06 |
Write Enable |
| 0x50 |
Volatile SR Write Enable |
| 0x04 |
Write Disable |
| 0x05 |
Read Status-1 |
| 0x01 |
Write Status-1 |
| 0x35 |
Read Status -2 |
| 0x31 |
Write Status-2 |
| 0x9F |
Read JEDEC-ID |
| 0x03 |
Read Data |
| 0x0B |
Fast Read Data |
| 0x3B |
Fast Read Dual Data |
| 0x6B |
Fast Read Quad Data |
| 0x13 |
Read Data 4-byte address |
| 0x0C |
Fast Read Data 4-byte |
| 0x3C |
Fast Read Dual Data 4-byte |
| 0x6C |
Fast Read Quad Data 4-byte |
| 0xBC |
Fast Read Dual IO Addr4 |
| 0xEC |
Fast Read Quad IO Addr4 |
| 0x02 |
Page Program |
| 0x32 |
Quad Page Program |
| 0x20 |
Sector Erase (4KB) |
| 0x52 |
Block Erase (32KB) |
| 0xD8 |
Block Erase (64KB) |
| 0x5A |
Read SFDP |
ntx number of commands to be sent.nresponse number of responses to be read after transmitting commands.
|
| Returns |
1 - if a previous transfer is not active and cmd_params is not a null pointer and ntx is not zero.0 - If any of the aforementioned conditions are false.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
None.
|
qmspi_read_fifo
| Prototype |
unsigned long qmspi_read_fifo(unsigned char *pdata, unsigned long byte_len);
|
| Description |
The function is used to read data from the QMSPI FIFO.
|
| Parameters |
pdata: pointer to a buffer.byte_len: buffer length.
|
| Returns |
Balue indicating the number of bytes read.
|
| Requires |
MCU must have the Quad SPI Master Controller.
|
| Notes |
The number of bytes read will always be equal to or less than the buffer length specified.
|
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